package top

import chisel3._
import chisel3.util._
import chisel3.stage.ChiselGeneratorAnnotation
import firrtl.options.TargetDirAnnotation
import system.MySoC
import utils._

object TopMain extends App {
  def parseArgs(info: String, args: Array[String]) : String = {
    var target = ""
    for(arg <- args) {
      if(arg.startsWith(info + "=") == true){
        target = arg
      }
    }
    require(target != "")
    target.substring(info.length + 1);
  }
  val platform = parseArgs("BOARD", args)

  val chosen_setting = platform match {
    case "sim" => Nil
    case "ysyx" => YsyxSettings()
  }
 
  chosen_setting.foreach(Settings.settings += _)


  if(platform == "sim"){
      (new chisel3.stage.ChiselStage).execute(
        Array("-X", "verilog", "--full-stacktrace"),
        Seq(ChiselGeneratorAnnotation(() => new MySoCSim()),
          TargetDirAnnotation("build/emu/verilog"))
      )
  } else {
    (new chisel3.stage.ChiselStage).execute(
      Array("-X", "verilog", "--full-stacktrace"),
      Seq(ChiselGeneratorAnnotation(() => new MySoC()),
        TargetDirAnnotation("build/soc/verilog"),
        firrtl.stage.RunFirrtlTransformAnnotation(new AddModulePrefix()),
        ModulePrefixAnnotation("ysyx_210718_")
    ))
  }
  
}
